1. Field of the Invention
The invention relates to a test method, and more particularly to a batch-test method with a chip tray.
2. Description of the Related Art
Recently, there a need for more efficient semiconductor device testing processes has arisen. A semiconductor device is generally subject to a wafer test and a chip test before it is shipped to a user. The wafer test is performed in a wafer state, while the chip test is performed in a chip state after the wafer is diced, assembled and packaged. The wafer test and chip test are performed in order to prevent possible inflow of defective chips in an assembly process, i.e., in order to best reject possible defective chips in a chip state.
In a conventional chip test procedure, a specific chip test apparatus is required and the chip test apparatus cannot be shared to test different chips, thus, the test cost increases. Moreover, the present chip test apparatus cannot test a large number of chips at the same time, and the chips need to be manually delivered to the chip test apparatus to process testing procedure. The described test method and apparatus not only waste time, but increase the risk of shipping delay. Furthermore, automated test procedure and apparatus are major stream in the present day, thus, how to design a appropriate test procedure and apparatus to be compatible to different types of chip is the most desirable in the present day.